1. Field of the Invention
The present invention relates but not limited to electronic devices, and in particular, to output buffers for driving signals on digital buses.
2. Description of Related Art
High speed bus output drivers or buffers are used to drive digital signals over a digital bus. The bus output buffer is an interface circuit for placing an integrated circuit's (IC's) internal digital signal onto the bus. Prior art output buffers typically have a pre-driver and a driver, with the pre-driver's output waveform controlling a slew rate of the driver. The slew rate is the rate of change of voltage (voltage change/time) that an output buffer can generate when the driver is changing its output signal from low-to-high (LH signal transition) or high-to-low (HL signal transition). An optimal slew rate is statically selected for the bus, and all the output buffers connected to the bus are selected to have a substantially similar slew rate to support high speed signal transfer on the bus.
Some of logic components of the output buffers, such as the driver, have an asymmetric response to rising and falling transitions of the waveforms of digital signals. As an illustration of this asymmetric response, there is shown in FIG. 1 two pre-driver output waveforms (PREDRVOUT) which are used to turn on and off a NMOS driver in an assisted gunning transceiver logic (AGTL+) output buffer. The first waveform 10 is identified by voltage breakpoints A, C, D, E and the second waveform 12 is identified by voltage breakpoints A′, C′, D′, E′. The maximum voltages at breakpoints A and E of waveform 10 and at breakpoints at A′ and E′ of waveform 12 illustrate how the supply voltage for the output buffer may vary. Switching by the pre-driver waveform to trigger the LH and HL transitions of the driver's output occurs approximately at a threshold voltage VTN (switch level) of a NMOS transistor of the driver. Hence, a LH switching delay period tSWLH is defined as the delay time period during which the pre-driver waveform's voltage decreases to reach the switching level voltage (transitions from source voltage to the threshold voltage VTN), after which the pre-driver waveform triggers the LH transition of the driver's output. A HL switching delay period tSWHL is defined as the time delay period during which the pre-driver waveform's voltage increases to reach the switching level voltage (transitions from ground to the threshold voltage VTN), after which the pre-driver waveform triggers the HL transition of the driver's output.
The term “TCO” or “clock-to-output delay” is defined as the delay between a data clock and a valid output signal from the driver. The time difference in the signal switching delay periods tSWLH and tSWHL means that there are different TCO delays for the LH and HL transitions of the output signal of the driver. The time difference between the signal switching delay periods tSWLH and tSWHL is defined to create “TCO LH/HL skew” in the output of the driver. Hence, digital pulse signals propagating through these asymmetric logic components of the output buffer cause the output signals of the driver to be either shortened or lengthened due to TCO LH/HL skew.
In FIG. 1 there is a time difference between the signal switching delay periods tSWLH and tSWHL of the driver with both pre-driver waveforms 10 and 12; hence, both create TCO LH/HL skew. However, there is a much greater time difference in the delay periods tSWLH and tSWHL for waveform 12 than for waveform 10, which in turn illustrates that the TCO LH/HL skew increases with increasing voltage swings of the signal transitions of the pre-driver waveform.
In the past, lower frequency digital bus output buffers tolerated a fairly significant amount (wide spread) of TCO HL/LH skew caused by PVT. But this wide spread TCO HL/LH skew directly limits the bus speed when bus frequency approaches to Ghz range. As digital bus frequency keeps increasing, the design specifications for output buffers require smaller amounts of TCO LH/HL skew. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art to reduce TCO LH/HL skew.